第7章 バックエンドを作る

リスト7.1: 目標のソースコード(sample_add.ll)

 1: define i32 @sample_add(i32 %a, i32 %b) nounwind readnone {
 2: entry:
 3:   %add = add nsw i32 %b, %a
 4:   ret i32 %add
 5: }

リスト7.2: 目標のソースコード(sample_call.ll)

 1: define i32 @add(i32 %a, i32 %b) nounwind readnone {
 2: entry:
 3:   %add = add nsw i32 %b, %a
 4:   ret i32 %add
 5: }
 6: 
 7: define i32 @sample_call() nounwind readnone {
 8: entry:
 9:   %call = tail call i32 @add(i32 1, i32 2)
10:   ret i32 %call
11: }

リスト7.3: TableGenのクラス定義

 1: class A { bit V = 0; }
 2: class B : A;
 3: class C : A {
 4:   string str = "hello";
 5: }
 6: class D : A {
 7:   let V = 1;
 8: }

リスト7.4: TableGenのクラスの実体化

 1: def X : A;
 2: def Y : C {
 3:   string str2 = "world";
 4: }
 5: let V = 2, str = "Hello World" in
 6:   def Z : C;
 7: let V = 3 in {
 8:   def ZZ : C;
 9:   let str = "Hello World!" in
10:     def ZZZ : C;
11: }

リスト7.5: TableGenでのレジスタ定義

 1: class SampleReg<bits<4> num, string n> : Register<n> {
 2:   field bits<4> num;
 3:   let Namespace = "Sample";
 4: }
 5: 
 6: // 汎用レジスタ
 7: def ZERO : SampleReg< 0, "ZERO">, DwarfRegNum<[0]>;
 8: def V0   : SampleReg< 1, "V0">,   DwarfRegNum<[1]>;
 9: def A0   : SampleReg< 2, "A0">,   DwarfRegNum<[2]>;
10: def A1   : SampleReg< 3, "A1">,   DwarfRegNum<[3]>;
11: def A2   : SampleReg< 4, "A2">,   DwarfRegNum<[4]>;
12: def A3   : SampleReg< 5, "A3">,   DwarfRegNum<[5]>;
13: def T0   : SampleReg< 6, "T0">,   DwarfRegNum<[6]>;
14: def T1   : SampleReg< 7, "T1">,   DwarfRegNum<[7]>;
15: def T2   : SampleReg< 8, "T2">,   DwarfRegNum<[8]>;
16: def T3   : SampleReg< 9, "T3">,   DwarfRegNum<[9]>;
17: def S0   : SampleReg< 10, "S0">,  DwarfRegNum<[10]>;
18: def S1   : SampleReg< 11, "S1">,  DwarfRegNum<[11]>;
19: def S2   : SampleReg< 12, "S2">,  DwarfRegNum<[12]>;
20: def S3   : SampleReg< 13, "S3">,  DwarfRegNum<[13]>;
21: def SP   : SampleReg< 14, "SP">,  DwarfRegNum<[14]>;
22: def RA   : SampleReg< 15, "RA">,  DwarfRegNum<[15]>;

リスト7.6: TableGenのレジスタクラス定義

 1: def CPURegs : RegisterClass<"Sample", [i32], 32, (add
 2:   // 戻り値と引数用レジスタ (Return values and Arguments registers)
 3:   V0, A0, A1, A2, A3,
 4:   // 呼び出し元待避レジスタ (Caller saved registers)
 5:   T0, T1, T2, T3,
 6:   // 呼び出し先待避レジスタ (Callee saved registers)
 7:   S0, S1, S2, S3,
 8:   // 予約レジスタ (Reserved registers)
 9:   ZERO, SP, RA)>;

リスト7.7: TableGenでの機能ユニット定義

 1: // 機能ユニット
 2: def ALU : FuncUnit;
 3: 
 4: // 命令スケジュール(Instruction Itinerary)
 5: def IICAlu    : InstrItinClass;
 6: def IICLoad   : InstrItinClass;
 7: def IICStore  : InstrItinClass;
 8: def IICBranch : InstrItinClass;
 9: def IICPseudo : InstrItinClass;
10: 
11: // Sampleターゲットのプロセッサスケジュール
12: def SampleGenericItineraries : ProcessorItineraries<[ALU], [], [
13:     InstrItinData<IICAlu    , [InstrStage<1,  [ALU]>]>,
14:     InstrItinData<IICLoad   , [InstrStage<1,  [ALU]>]>,
15:     InstrItinData<IICStore  , [InstrStage<1,  [ALU]>]>,
16:     InstrItinData<IICBranch , [InstrStage<1,  [ALU]>]>,
17:     InstrItinData<IICPseudo , [InstrStage<1,  [ALU]>]>
18: ]>;

リスト7.8: TableGenでの呼び出し規約定義

 1: // Sample Calling Convention
 2: def CC_Sample : CallingConv<[
 3:   // i8/i16型の引数はi32型に昇格する
 4:   CCIfType<[i8, i16], CCPromoteToType<i32>>,
 5: 
 6:   // 整数型はAレジスタに渡す
 7:   CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3]>>,
 8: ]>;
 9: 
10: def RetCC_Sample : CallingConv<[
11:   // i32型はV0レジスタに渡す
12:   CCIfType<[i32], CCAssignToReg<[V0]>>
13: ]>;
14: 
15: // 呼び出し先待避レジスタ(Callee-saved register)
16: def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "S%u", 3, 0), RA)>;

リスト7.9: TableGenでのターゲット定義

 1: def SampleInstrInfo : InstrInfo;
 2: 
 3: def : Processor<"sample32", SampleGenericItineraries, []>;
 4: 
 5: def SampleAsmWriter : AsmWriter {
 6:   string AsmWriterClassName  = "InstPrinter";
 7:   bit isMCAsmWriter = 1;
 8: }
 9: 
10: def Sample : Target {
11:   let InstructionSet = SampleInstrInfo;
12:   let AssemblyWriters = [SampleAsmWriter];
13: }

リスト7.10: TableGenでの命令のフォーマットテンプレート定義

 1: class Format<bits<3> val> {
 2:   bits<3> Value = val;
 3: }
 4: 
 5: def Pseudo    : Format<0>;
 6: def FormReg0  : Format<1>;
 7: def FormReg1  : Format<2>;
 8: def FormReg2  : Format<3>;
 9: def FormReg3  : Format<4>;
10: 
11: // 共通命令フォーマット
12: class SampleInst<dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin, Format f>
13:       : Instruction {
14:   field bits<32> Inst;
15:   Format Form = f;
16: 
17:   bits<8> Opcode = 0;
18: 
19:   let Namespace = "Sample";
20:   let Size = 4;
21:   let Inst{31-24} = Opcode;
22:   let OutOperandList = outs;
23:   let InOperandList  = ins;
24:   let AsmString   = asmstr;
25:   let Pattern     = pattern;
26:   let Itinerary   = itin;
27: 
28:   bits<3> FormBits = Form.Value;
29: 
30:   let DecoderNamespace = "Sample";
31: 
32:   field bits<32> SoftFail = 0;
33: }

リスト7.11: レジスタ数毎のフォーマット定義

 1: // 0レジスタフォーマットの定義
 2: class SampleInstFormReg0<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin>
 3:       : SampleInst<outs, ins, asmstr, pattern, itin, FormReg0> {
 4:   bits<24> other;
 5: 
 6:   let Opcode = op;
 7: 
 8:   let Inst{23-0} = other;
 9: }
10: 
11: // 1レジスタフォーマットの定義
12: class SampleInstFormReg1<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin>
13:       : SampleInst<outs, ins, asmstr, pattern, itin, FormReg1> {
14:   bits<4> rc;
15:   bits<20> other;
16: 
17:   let Opcode = op;
18: 
19:   let Inst{23-20} = rc;
20:   let Inst{19-0}  = other;
21: }
22: 
23: // 3レジスタフォーマットの定義
24: class SampleInstFormReg3<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin>
25:       : SampleInst<outs, ins, asmstr, pattern, itin, FormReg3> {
26:   bits<4> rc;
27:   bits<4> ra;
28:   bits<4> rb;
29:   bits<12> other;
30: 
31:   let Opcode = op;
32: 
33:   let Inst{23-20} = rc;
34:   let Inst{19-16} = ra;
35:   let Inst{15-12} = rb;
36:   let Inst{11-0}  = other;
37: }
38: 
39: // 疑似命令の定義
40: class SamplePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
41:   SampleInst<outs, ins, asmstr, pattern, IICPseudo, Pseudo> {
42:   let isCodeGenOnly = 1;
43:   let isPseudo = 1;
44: }

リスト7.12: TableGenでのadd，sub命令定義

 1: // 3つのオペランドを取る算術命令用のフォーマット定義
 2: class ArithLogicInst<bits<8> op, string asmstr, SDNode OpNode, InstrItinClass itin, RegisterClass RC>
 3:   : SampleInstFormReg3<op, (outs RC:$rc), (ins RC:$ra, RC:$rb),
 4:                       !strconcat(asmstr, "\t$rc, $ra, $rb"),
 5:                       [(set RC:$rc, (OpNode RC:$ra, RC:$rb))], itin> {
 6: }
 7: 
 8: def ADD : ArithLogicInst<0x05, "add", add, IICAlu, CPURegs>;
 9: def SUB : ArithLogicInst<0x06, "sub", sub, IICAlu, CPURegs>;

リスト7.13: TableGenでのmove命令定義

 1: // 符号付き20bit整数
 2: def immSExt20 : PatLeaf<(imm), [{ return isInt<20>(N->getSExtValue()); }]>;
 3: 
 4: // 即値ロード用のオペランド. 20bit
 5: // 19-0: 符号付き20bit整数
 6: // EncoderMethod: bit列から符号付き20bit整数を取得
 7: def movetarget : Operand<i32> {
 8:   let EncoderMethod = "getMoveTargetOpValue";
 9: }
10: 
11: // 即値ロード命令(Load Immediate)
12: class LoadI<bits<8> op, string asmstr>:
13:   SampleInstFormReg1<op, (outs CPURegs:$rc), (ins movetarget:$other),
14:      !strconcat(asmstr, "\t$rc, $other"), [(set CPURegs:$rc, immSExt20:$other)], IICLoad> {
15:   let DecoderMethod = "DecodeMoveTarget";
16: }
17: 
18: def MOVE : LoadI<0x02, "move">;

リスト7.14: TableGenでのcall命令定義

 1: // iPTR型のオペランドを1つ取るという制約条件
 2: def SDT_SampleCall : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
 3: 
 4: // Sampleターゲットの関数呼び出し命令のSDNode
 5: def SampleCall : SDNode<"SampleISD::Call", SDT_SampleCall,
 6:                          [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
 7:                           SDNPVariadic]>;
 8: 
 9: def : Pat<(SampleCall (i32 tglobaladdr:$dst)),
10:           (CALL tglobaladdr:$dst)>;
11: def : Pat<(SampleCall (i32 texternalsym:$dst)),
12:           (CALL texternalsym:$dst)>;
13: 
14: def calltarget : Operand<iPTR> {
15:   let EncoderMethod = "getCallTargetOpValue";
16: }
17: 
18: class Call<bits<8> op, string asmstr>:
19:   SampleInstFormReg0<op, (outs), (ins calltarget:$other, variable_ops),
20:      !strconcat(asmstr, "\t$other"), [(SampleCall imm:$other)],
21:      IICBranch> {
22:   let isCall=1;
23:   let DecoderMethod = "DecodeCallTarget";
24: }
25: 
26: def CALL : Call<0x03, "call">;

リスト7.15: TableGenでのret命令定義

 1: def SDT_SampleRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 2: def SampleRet : SDNode<"SampleISD::Ret", SDT_SampleRet,
 3:                        [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 4: 
 5: class RetInst<bits<8> op, string asmstr>:
 6:   SampleInstFormReg1<op, (outs), (ins CPURegs:$rc),
 7:      !strconcat(asmstr, "\t$rc"), [(SampleRet CPURegs:$rc)], IICBranch> {
 8:   let isBranch=1;
 9:   let isTerminator=1;
10:   let isBarrier=1;
11:   let isReturn=1;
12: }
13: 
14: def RET : RetInst<0x04, "ret">;

リスト7.16: TableGenでの1レジスタ命令定義

 1: // アドレスオペランド
 2: def mem : Operand<i32> {
 3:   let PrintMethod = "printMemOperand";
 4:   let MIOperandInfo = (ops CPURegs, i16imm);
 5:   let EncoderMethod = "getMemEncoding";
 6: }
 7: 
 8: def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
 9: 
10: // Load/Store命令共通フォーマット
11: class FMem<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin>
12:       : SampleInstFormReg1<op, outs, ins, asmstr, pattern, itin> {
13:   bits<20> addr;
14:   let Inst{19-0}  = addr;
15:   let DecoderMethod = "DecodeMem";
16: }
17: 
18: // Load命令
19: let canFoldAsLoad = 1 in
20: class LoadM<bits<8> op, string asmstr, RegisterClass RC>:
21:   FMem<op, (outs RC:$rc), (ins mem:$addr),
22:      !strconcat(asmstr, "\t$rc, $addr"),
23:      [(set RC:$rc, (load addr:$addr))], IICLoad>;
24: 
25: // Store命令
26: class StoreM<bits<8> op, string asmstr, RegisterClass RC>:
27:   FMem<op, (outs), (ins RC:$rc, mem:$addr),
28:      !strconcat(asmstr, "\t$rc, $addr"),
29:      [(store RC:$rc, addr:$addr)], IICStore>;
30: 
31: def LOAD  : LoadM<0x00, "load", CPURegs>;
32: def STORE : StoreM<0x01, "store", CPURegs>;

リスト7.17: ターゲットのMakefile

 1: LEVEL = ../../..
 2: LIBRARYNAME = LLVMSampleCodeGen
 3: TARGET = Sample
 4: 
 5: # Make sure that tblgen is run, first thing.
 6: BUILT_SOURCES = SampleGenRegisterInfo.inc SampleGenInstrInfo.inc \
 7:                 SampleGenAsmWriter.inc SampleGenCodeEmitter.inc \
 8:                 SampleGenDAGISel.inc SampleGenCallingConv.inc \
 9:                 SampleGenSubtargetInfo.inc SampleGenMCCodeEmitter.inc \
10:                 SampleGenEDInfo.inc SampleGenDisassemblerTables.inc
11: 
12: DIRS = InstPrinter Disassembler TargetInfo MCTargetDesc
13: 
14: include $(LEVEL)/Makefile.common

リスト7.18: SampleTargetMachineのクラス定義

 1: class SampleTargetMachine : public LLVMTargetMachine {
 2:   const DataLayout DL;
 3:   SampleSubtarget Subtarget;
 4:   SampleInstrInfo InstrInfo;
 5:   SampleFrameLowering FrameLowering;
 6:   SampleTargetLowering TLInfo;
 7:   SampleSelectionDAGInfo TSInfo;
 8: 
 9:  public:
10:   SampleTargetMachine(const Target &T, StringRef TT,
11:                       StringRef CPU, StringRef FS, const TargetOptions &Options,
12:                       Reloc::Model RM, CodeModel::Model CM,
13:                       CodeGenOpt::Level OL);
14: 
15:   virtual const SampleInstrInfo *getInstrInfo() const {
16:     return &InstrInfo;
17:   }
18:   virtual const SampleSubtarget *getSubtargetImpl() const {
19:     return &Subtarget;
20:   }
21:   virtual const SampleRegisterInfo *getRegisterInfo() const {
22:     return &InstrInfo.getRegisterInfo();
23:   }
24:   virtual const DataLayout *getDataLayout() const {
25:     return &DL;
26:   }
27:   virtual const SampleTargetLowering *getTargetLowering() const {
28:     return &TLInfo;
29:   }
30:   virtual const SampleFrameLowering *getFrameLowering() const{
31:     return &FrameLowering;
32:   }
33:   virtual const SampleSelectionDAGInfo* getSelectionDAGInfo() const {
34:     return &TSInfo;
35:   }
36: 
37:   virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
38: };

リスト7.19: SampleTargetMachine::createPassConfig

 1: TargetPassConfig *SampleTargetMachine::createPassConfig(PassManagerBase &PM) {
 2:   return new SamplePassConfig(this, PM);
 3: }

リスト7.20: SamplePassConfigクラス

 1: class SamplePassConfig : public TargetPassConfig {
 2:  public:
 3:   SamplePassConfig(SampleTargetMachine *TM, PassManagerBase &PM)
 4:     : TargetPassConfig(TM, PM) {}
 5: 
 6:   SampleTargetMachine &getSampleTargetMachine() const {
 7:     return getTM<SampleTargetMachine>();
 8:   }
 9: 
10:   virtual bool addInstSelector();
11: };
12: 
13: bool SamplePassConfig::addInstSelector() {
14:   addPass(createSampleISelDag(getSampleTargetMachine()));
15:   return false;
16: }

リスト7.21: SampleSubtargetのクラス定義

 1: class SampleSubtarget : public SampleGenSubtargetInfo {
 2:   virtual void anchor() {};
 3:   bool ExtendedInsts;
 4:  public:
 5: 
 6:   SampleSubtarget(const std::string &TT, const std::string &CPU,
 7:                   const std::string &FS);
 8: 
 9:   // TableGenにより自動生成
10:   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
11: };

リスト7.22: SampleInstrInfoのクラス定義

 1: class SampleInstrInfo : public SampleGenInstrInfo {
 2:   SampleTargetMachine &TM;
 3:   const SampleRegisterInfo RI;
 4:  public:
 5:   explicit SampleInstrInfo(SampleTargetMachine &TM);
 6: 
 7:   virtual const SampleRegisterInfo &getRegisterInfo() const;
 8: 
 9:   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
10:                                        int &FrameIndex) const;
11: 
12:   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
13:                                       int &FrameIndex) const;
14: 
15:   virtual void copyPhysReg(MachineBasicBlock &MBB,
16:                            MachineBasicBlock::iterator MI, DebugLoc DL,
17:                            unsigned DestReg, unsigned SrcReg,
18:                            bool KillSrc) const;
19:   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
20:                                    MachineBasicBlock::iterator MBBI,
21:                                    unsigned SrcReg, bool isKill, int FrameIndex,
22:                                    const TargetRegisterClass *RC,
23:                                    const TargetRegisterInfo *TRI) const;
24: 
25:   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
26:                                     MachineBasicBlock::iterator MBBI,
27:                                     unsigned DestReg, int FrameIndex,
28:                                     const TargetRegisterClass *RC,
29:                                     const TargetRegisterInfo *TRI) const;
30: 
31:   // 分岐解析
32:   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
33:                              MachineBasicBlock *&FBB,
34:                              SmallVectorImpl<MachineOperand> &Cond,
35:                              bool AllowModify) const;
36: 
37:   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
38: 
39:   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
40:                                 MachineBasicBlock *FBB,
41:                                 const SmallVectorImpl<MachineOperand> &Cond,
42:                                 DebugLoc DL) const;
43: };

リスト7.23: SampleInstrInfo::copyPhysReg

 1: void SampleInstrInfo::
 2: copyPhysReg(MachineBasicBlock &MBB,
 3:             MachineBasicBlock::iterator I, DebugLoc DL,
 4:             unsigned DestReg, unsigned SrcReg,
 5:             bool KillSrc) const {
 6:   unsigned Opc = Sample::ADD;
 7:   unsigned ZeroReg = Sample::ZERO;
 8:   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
 9: 
10:   if (DestReg)
11:     MIB.addReg(DestReg, RegState::Define);
12: 
13:   if (ZeroReg)
14:     MIB.addReg(ZeroReg);
15: 
16:   if (SrcReg)
17:     MIB.addReg(SrcReg, getKillRegState(KillSrc));
18: }

リスト7.24: SampleInstrInfo::storeRegToStackSlot

 1: void SampleInstrInfo::
 2: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 3:                     unsigned SrcReg, bool isKill, int FI,
 4:                     const TargetRegisterClass *RC,
 5:                     const TargetRegisterInfo *TRI) const {
 6:   DebugLoc DL;
 7:   if (I != MBB.end()) DL = I->getDebugLoc();
 8:   MachineFunction &MF = *MBB.getParent();
 9:   MachineFrameInfo &MFI = *MF.getFrameInfo();
10: 
11:   MachineMemOperand *MMO =
12:     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
13:                             MachineMemOperand::MOStore,
14:                             MFI.getObjectSize(FI),
15:                             MFI.getObjectAlignment(FI));
16: 
17:   BuildMI(MBB, I, DL, get(Sample::STORE))
18:       .addReg(SrcReg, getKillRegState(isKill))
19:       .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
20: }

リスト7.25: SampleInstrInfo::loadRegFromStackSlot

 1: void SampleInstrInfo::
 2: loadRegFromStackSlot(MachineBasicBlock &MBB,
 3:                      MachineBasicBlock::iterator MI,
 4:                      unsigned DestReg, int FI,
 5:                      const TargetRegisterClass *RC,
 6:                      const TargetRegisterInfo *TRI) const {
 7:   DebugLoc DL;
 8:   if (MI != MBB.end()) DL = MI->getDebugLoc();
 9:   MachineFunction &MF = *MBB.getParent();
10:   MachineFrameInfo &MFI = *MF.getFrameInfo();
11: 
12:   MachineMemOperand *MMO =
13:     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
14:                             MachineMemOperand::MOLoad,
15:                             MFI.getObjectSize(FI),
16:                             MFI.getObjectAlignment(FI));
17: 
18:   BuildMI(MBB, MI, DL, get(Sample::LOAD))
19:       .addReg(DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);
20: }

リスト7.26: SampleRegisterInfoのクラス定義

 1: struct SampleRegisterInfo : public SampleGenRegisterInfo {
 2:   const TargetInstrInfo &TII;
 3: 
 4:   SampleRegisterInfo(const TargetInstrInfo &tii);
 5: 
 6:   const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 7:   const uint32_t *getCallPreservedMask(CallingConv::ID) const;
 8: 
 9:   BitVector getReservedRegs(const MachineFunction &MF) const;
10: 
11:   void eliminateCallFramePseudoInstr(MachineFunction &MF,
12:                                      MachineBasicBlock &MBB,
13:                                      MachineBasicBlock::iterator I) const;
14: 
15:   void eliminateFrameIndex(MachineBasicBlock::iterator II,
16:                            int SPAdj, RegScavenger *RS = NULL) const;
17: 
18:   unsigned getFrameRegister(const MachineFunction &MF) const;
19: };

リスト7.27: SampleRegisterInfo::eliminateFrameIndex

 1: void SampleRegisterInfo::
 2: eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 3:                     RegScavenger *RS) const {
 4:   MachineInstr &MI = *II;
 5:   const MachineFunction &MF = *MI.getParent()->getParent();
 6: 
 7:   // フレームインデックスを探す
 8:   unsigned opIndex;
 9:   for (opIndex = 0; opIndex < MI.getNumOperands(); opIndex++) {
10:     if (MI.getOperand(opIndex).isFI()) break;
11:   }
12:   assert(opIndex < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
13: 
14:   int FrameIndex = MI.getOperand(opIndex).getIndex();
15:   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
16:   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
17:   int64_t Offset = spOffset + stackSize + MI.getOperand(opIndex+1).getImm();
18:   unsigned FrameReg = Sample::SP;
19: 
20:   // レジスタと即値を変更する
21:   MI.getOperand(opIndex).ChangeToRegister(FrameReg, false);
22:   MI.getOperand(opIndex+1).ChangeToImmediate(Offset);
23: }

リスト7.28: SampleMachineFunctionInfoのクラス定義

 1: class SampleMachineFunctionInfo : public MachineFunctionInfo {
 2:   virtual void anchor();
 3: 
 4:  public:
 5:   SampleMachineFunctionInfo(MachineFunction& MF) {}
 6: };

リスト7.29: SampleDAGToDAGISelのクラス定義

 1: class SampleDAGToDAGISel : public SelectionDAGISel {
 2:   SampleTargetMachine &TM;
 3:   const SampleSubtarget &Subtarget;
 4: 
 5:  public:
 6:   explicit SampleDAGToDAGISel(SampleTargetMachine &tm) :
 7:   SelectionDAGISel(tm),
 8:   TM(tm),
 9:   Subtarget(tm.getSubtarget<SampleSubtarget>()) {}
10: 
11:   // パス名
12:   virtual const char *getPassName() const {
13:     return "Sample DAG->DAG Pattern Instruction Selection";
14:   }
15: 
16: private:
17:   // TableGenで自動生成されたメソッドをインクルード
18:   #include "SampleGenDAGISel.inc"
19: 
20:   const SampleTargetMachine &getTargetMachine() {
21:     return static_cast<const SampleTargetMachine &>(TM);
22:   }
23: 
24:   const SampleInstrInfo *getInstrInfo() {
25:     return getTargetMachine().getInstrInfo();
26:   }
27: 
28:   SDNode *Select(SDNode *N);
29: 
30:   // Complex Pattern.
31:   bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
32: };

リスト7.30: SampleDAGToDAGISel::Select

 1: SDNode* SampleDAGToDAGISel::Select(SDNode *Node) {
 2:   // TableGenにより自動生成された関数を呼び出す
 3:   SDNode *ResNode = SelectCode(Node);
 4:   return ResNode;
 5: }

リスト7.31: SampleDAGToDAGISel::SelectAddr

 1: bool SampleDAGToDAGISel::
 2: SelectAddr(SDValue N, SDValue &Base, SDValue &Offset) {
 3:   EVT ValTy = N.getValueType();
 4: 
 5:   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
 6:     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
 7:     Offset = CurDAG->getTargetConstant(0, ValTy);
 8:     return true;
 9:   }
10: 
11:   llvm_unreachable("Unknown pattern");
12:   return true;
13: }

リスト7.32: SampleTargetLoweringのクラス定義

 1: class SampleTargetLowering : public TargetLowering {
 2:   const SampleSubtarget &Subtarget;
 3: 
 4:  public:
 5:   explicit SampleTargetLowering(SampleTargetMachine &TM);
 6: 
 7:   // Customで指定した操作のLowering
 8:   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
 9: 
10:   // 引数のLowering
11:   virtual SDValue
12:   LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
13:                        bool isVarArg,
14:                        const SmallVectorImpl<ISD::InputArg> &Ins,
15:                        DebugLoc dl, SelectionDAG &DAG,
16:                        SmallVectorImpl<SDValue> &InVals) const;
17: 
18:   // 関数呼び出しのLowering
19:   virtual SDValue
20:   LowerCall(CallLoweringInfo &CLI,
21:             SmallVectorImpl<SDValue> &InVals) const;
22: 
23:   // 戻り値のLowering
24:   virtual SDValue
25:   LowerCallResult(SDValue Chain, SDValue InFlag,
26:                   CallingConv::ID CallConv, bool isVarArg,
27:                   const SmallVectorImpl<ISD::InputArg> &Ins,
28:                   DebugLoc dl, SelectionDAG &DAG,
29:                   SmallVectorImpl<SDValue> &InVals) const;
30: 
31:   // returnのLowering
32:   virtual SDValue
33:   LowerReturn(SDValue Chain,
34:               CallingConv::ID CallConv, bool isVarArg,
35:               const SmallVectorImpl<ISD::OutputArg> &Outs,
36:               const SmallVectorImpl<SDValue> &OutVals,
37:               DebugLoc dl, SelectionDAG &DAG) const;
38: };

リスト7.33: SampleTargetLoweringのコンストラクタ

 1: SampleTargetLowering::
 2: SampleTargetLowering(SampleTargetMachine &TM)
 3:   : TargetLowering(TM, new TargetLoweringObjectFileELF()),
 4:     Subtarget(*TM.getSubtargetImpl()) {
 5: 
 6:   // booleanをどう表すかを定義
 7:   setBooleanContents(ZeroOrOneBooleanContent);
 8:   setBooleanVectorContents(ZeroOrOneBooleanContent);
 9: 
10:   // ターゲットで利用できるレジスタを登録
11:   addRegisterClass(MVT::i32, Sample::CPURegsRegisterClass);
12: 
13:   // (符号)拡張ロード命令が対応していない型の操作方法を登録
14:   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
15:   setLoadExtAction(ISD::EXTLOAD,  MVT::i8,  Promote);
16:   setLoadExtAction(ISD::EXTLOAD,  MVT::i16, Promote);
17:   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
18:   setLoadExtAction(ISD::ZEXTLOAD, MVT::i8,  Promote);
19:   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Promote);
20:   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
21:   setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Promote);
22:   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Promote);
23: 
24:   // 関数のアラインメント
25:   setMinFunctionAlignment(2);
26: 
27:   // スタックポインタのレジスタを指定
28:   setStackPointerRegisterToSaveRestore(Sample::SP);
29: 
30:   // レジスタの操作方法を計算
31:   computeRegisterProperties();
32: }

リスト7.34: SampleTargetLowering::LowerFormalArguments

 1: SDValue SampleTargetLowering::
 2: LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
 3:                      bool isVarArg,
 4:                      const SmallVectorImpl<ISD::InputArg> &Ins,
 5:                      DebugLoc dl, SelectionDAG &DAG,
 6:                      SmallVectorImpl<SDValue> &InVals) const {
 7:   MachineFunction &MF = DAG.getMachineFunction();
 8:   MachineFrameInfo *MFI = MF.getFrameInfo();
 9:   MachineRegisterInfo &RegInfo = MF.getRegInfo();
10: 
11:   // 引数を格納する
12:   SmallVector<CCValAssign, 16> ArgLocs;
13:   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
14:                  getTargetMachine(), ArgLocs, *DAG.getContext());
15:   CCInfo.AnalyzeFormalArguments(Ins, CC_Sample);
16: 
17:   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
18:     CCValAssign &VA = ArgLocs[i];
19:     if (VA.isRegLoc()) {
20:       // 引数がレジスタ経由で渡された場合
21:       EVT RegVT = VA.getLocVT();
22:       // 使用するレジスタクラスを指定
23:       const TargetRegisterClass *RC = Sample::CPURegsRegisterClass;
24: 
25:       if (VA.getLocInfo() != CCValAssign::Full) {
26:         llvm_unreachable("not supported yet");
27:       }
28: 
29:       // 仮想レジスタを作成
30:       unsigned VReg = RegInfo.createVirtualRegister(RC);
31:       RegInfo.addLiveIn(VA.getLocReg(), VReg);
32:       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
33:       InVals.push_back(ArgValue);
34:     } else { // VA.isRegLoc()
35:       // 引数がスタック経由で渡された場合
36:       assert(VA.isMemLoc());
37: 
38:       // フレームインデックスを作成する
39:       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
40:       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
41: 
42:       // スタックから引数を取得するためにloadノードを作成する
43:       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
44:       InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
45:                                    MachinePointerInfo::getFixedStack(FI),
46:                                    false, false, false, 0));
47:     }
48:   }
49: 
50:   return Chain;
51: }

リスト7.35: SampleTargetLowering::LowerCall

 1: SDValue SampleTargetLowering::
 2: LowerCall(CallLoweringInfo &CLI,
 3:           SmallVectorImpl<SDValue> &InVals) const {
 4:   SelectionDAG &DAG                     = CLI.DAG;
 5:   DebugLoc &dl                          = CLI.DL;
 6:   SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
 7:   SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
 8:   SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
 9:   SDValue InChain                       = CLI.Chain;
10:   SDValue Callee                        = CLI.Callee;
11:   bool &isTailCall                      = CLI.IsTailCall;
12:   CallingConv::ID CallConv              = CLI.CallConv;
13:   bool isVarArg                         = CLI.IsVarArg;
14: 
15:   // 末尾呼び出しは未対応
16:   isTailCall = false;
17: 
18:   // 関数のオペランドを解析してオペランドをレジスタに割り当てる
19:   SmallVector<CCValAssign, 16> ArgLocs;
20:   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
21:              getTargetMachine(), ArgLocs, *DAG.getContext());
22: 
23:   CCInfo.AnalyzeCallOperands(Outs, CC_Sample);
24: 
25:   // スタックを何Byte使っているか取得
26:   unsigned NumBytes = CCInfo.getNextStackOffset();
27: 
28:   // 関数呼び出し開始のNode
29:   InChain = DAG.getCALLSEQ_START(InChain,
30:                                  DAG.getConstant(NumBytes, getPointerTy(), true));
31: 
32:   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
33:   SDValue StackPtr;
34: 
35:   // 引数をRegsToPassに追加していく
36:   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
37:     SDValue Arg = OutVals[i];
38:     CCValAssign &VA = ArgLocs[i];
39:     ISD::ArgFlagsTy Flags = Outs[i].Flags;
40: 
41:     // 引数が数値
42:     if (Flags.isByVal()) {
43:       assert(Flags.getByValSize() &&
44:              "ByVal args of size 0 should have been ignored by front-end.");
45:       llvm_unreachable("ByVal arguments are not supported");
46:       continue;
47:     }
48: 
49:     // 必要に応じてPromoteする
50:     switch (VA.getLocInfo()) {
51:       default: llvm_unreachable("Unknown loc info!");
52:       case CCValAssign::Full: break;
53:       case CCValAssign::SExt:
54:         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
55:         break;
56:       case CCValAssign::ZExt:
57:         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
58:         break;
59:       case CCValAssign::AExt:
60:         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
61:         break;
62:     }
63: 
64:     // レジスタ経由の引数はRegsToPassに追加
65:     if (VA.isRegLoc()) {
66:       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
67:     } else {
68:       assert(VA.isMemLoc());
69:       llvm_unreachable("MemLoc arguments are not supported");
70:     }
71:   }
72: 
73:   // レジスタをコピーするノードを作成
74:   SDValue InFlag;
75:   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
76:     InChain = DAG.getCopyToReg(InChain, dl, RegsToPass[i].first,
77:                              RegsToPass[i].second, InFlag);
78:     InFlag = InChain.getValue(1);
79:   }
80: 
81:   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
82:     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
83:   } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
84:     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
85:   }
86: 
87:   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
88:   SmallVector<SDValue, 8> Ops;
89:   Ops.push_back(InChain);
90:   Ops.push_back(Callee);
91: 
92:   // 引数のレジスタをリストに追加
93:   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
94:     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
95:                                   RegsToPass[i].second.getValueType()));
96:   }
97: 
98:   if (InFlag.getNode())
99:     Ops.push_back(InFlag);
100: 
101:   InChain = DAG.getNode(SampleISD::Call, dl, NodeTys, &Ops[0], Ops.size());
102:   InFlag = InChain.getValue(1);
103: 
104:   // 関数呼び出し終了のNode
105:   InChain = DAG.getCALLSEQ_END(InChain,
106:                                DAG.getConstant(NumBytes, getPointerTy(), true),
107:                                DAG.getConstant(0, getPointerTy(), true),
108:                                InFlag);
109:   InFlag = InChain.getValue(1);
110: 
111:   // 戻り値の処理
112:   return LowerCallResult(InChain, InFlag, CallConv, isVarArg,
113:                          Ins, dl, DAG, InVals);
114: }

リスト7.36: SampleTargetLowering::LowerCallResult

 1: SDValue SampleTargetLowering::
 2: LowerCallResult(SDValue Chain, SDValue InFlag,
 3:                 CallingConv::ID CallConv, bool isVarArg,
 4:                 const SmallVectorImpl<ISD::InputArg> &Ins,
 5:                 DebugLoc dl, SelectionDAG &DAG,
 6:                 SmallVectorImpl<SDValue> &InVals) const {
 7:   SmallVector<CCValAssign, 16> RVLocs;
 8:   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 9:              getTargetMachine(), RVLocs, *DAG.getContext());
10: 
11:   CCInfo.AnalyzeCallResult(Ins, RetCC_Sample);
12: 
13:   // 結果レジスタをコピー
14:   for (unsigned i = 0; i != RVLocs.size(); ++i) {
15:     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
16:                                RVLocs[i].getValVT(), InFlag).getValue(1);
17:     InFlag = Chain.getValue(2);
18:     InVals.push_back(Chain.getValue(0));
19:   }
20: 
21:   return Chain;
22: }

リスト7.37: SampleTargetLowering::LowerReturn

 1: SDValue SampleTargetLowering::
 2: LowerReturn(SDValue Chain,
 3:             CallingConv::ID CallConv, bool isVarArg,
 4:             const SmallVectorImpl<ISD::OutputArg> &Outs,
 5:             const SmallVectorImpl<SDValue> &OutVals,
 6:             DebugLoc dl, SelectionDAG &DAG) const {
 7: 
 8:   SmallVector<CCValAssign, 16> RVLocs;
 9:   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
10:              getTargetMachine(), RVLocs, *DAG.getContext());
11: 
12:   // 戻り値を解析する
13:   CCInfo.AnalyzeReturn(Outs, RetCC_Sample);
14: 
15:   // この関数で最初の戻り値の場合はレジスタをliveoutに追加
16:   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
17:     for (unsigned i = 0; i != RVLocs.size(); ++i)
18:       if (RVLocs[i].isRegLoc())
19:         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
20:   }
21: 
22:   SDValue Flag;
23: 
24:   // 戻り値をレジスタにコピーするノードを作成
25:   for (unsigned i = 0; i != RVLocs.size(); ++i) {
26:     CCValAssign &VA = RVLocs[i];
27:     assert(VA.isRegLoc() && "Can only return in registers!");
28: 
29:     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
30:                              OutVals[i], Flag);
31: 
32:     Flag = Chain.getValue(1);
33:   }
34: 
35:   // 常に "ret $ra" を生成
36:   if (Flag.getNode())
37:     return DAG.getNode(SampleISD::Ret, dl, MVT::Other,
38:                        Chain, DAG.getRegister(Sample::RA, MVT::i32), Flag);
39:   else // Return Void
40:     return DAG.getNode(SampleISD::Ret, dl, MVT::Other,
41:                        Chain, DAG.getRegister(Sample::RA, MVT::i32));
42: }

リスト7.38: SampleSelectionDAGInfoのクラス定義

 1: class SampleSelectionDAGInfo : public TargetSelectionDAGInfo {
 2: public:
 3:   explicit SampleSelectionDAGInfo(const SampleTargetMachine &TM);
 4:   ~SampleSelectionDAGInfo();
 5: };

リスト7.39: SampleFrameLoweringのクラス定義

 1: class SampleFrameLowering : public TargetFrameLowering {
 2:  protected:
 3:   const SampleSubtarget &STI;
 4: 
 5:  public:
 6:   explicit SampleFrameLowering(const SampleSubtarget &sti)
 7:       : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
 8:   }
 9: 
10:   void emitPrologue(MachineFunction &MF) const;
11:   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
12:   bool hasFP(const MachineFunction &MF) const;
13: };

リスト7.40: SampleFrameLowering::emitPrologue

 1: void SampleFrameLowering::
 2: emitPrologue(MachineFunction &MF) const {
 3:   MachineBasicBlock &MBB   = MF.front();
 4:   MachineFrameInfo *MFI = MF.getFrameInfo();
 5: 
 6:   const SampleInstrInfo &TII =
 7:     *static_cast<const SampleInstrInfo*>(MF.getTarget().getInstrInfo());
 8: 
 9:   MachineBasicBlock::iterator MBBI = MBB.begin();
10:   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
11: 
12:   // 実装を簡単にするため固定サイズのスタック割り当て(4byte x レジスタ数)
13:   uint64_t StackSize = 4 * 16;
14: 
15:   // スタックサイズを保存
16:   MFI->setStackSize(StackSize);
17: 
18:   // スタックを伸ばす命令を生成
19:   BuildMI(MBB, MBBI, dl, TII.get(Sample::MOVE), Sample::T0)
20:       .addImm(-StackSize);
21:   BuildMI(MBB, MBBI, dl, TII.get(Sample::ADD), Sample::SP)
22:       .addReg(Sample::SP)
23:       .addReg(Sample::T0);
24: }

リスト7.41: SampleFrameLowering::emitEpilogue

 1: void SampleFrameLowering::
 2: emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
 3:   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
 4:   MachineFrameInfo *MFI            = MF.getFrameInfo();
 5:   const SampleInstrInfo &TII =
 6:     *static_cast<const SampleInstrInfo*>(MF.getTarget().getInstrInfo());
 7:   DebugLoc dl = MBBI->getDebugLoc();
 8: 
 9:   // FrameInfoからスタックサイズを取得
10:   uint64_t StackSize = MFI->getStackSize();
11: 
12:   // スタックを戻す命令を生成
13:   BuildMI(MBB, MBBI, dl, TII.get(Sample::MOVE), Sample::T0)
14:       .addImm(StackSize);
15:   BuildMI(MBB, MBBI, dl, TII.get(Sample::ADD), Sample::SP)
16:       .addReg(Sample::SP)
17:       .addReg(Sample::T0);
18: }

リスト7.42: SampleAsmPrinterのクラス定義

 1: class SampleAsmPrinter : public AsmPrinter {
 2:  public:
 3:   SampleAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
 4:       : AsmPrinter(TM, Streamer) {}
 5: 
 6:   virtual const char *getPassName() const {
 7:     return "Sample Assembly Printer";
 8:   }
 9: 
10:   void EmitInstruction(const MachineInstr *MI);
11: };

リスト7.43: SampleAsmPrinter::EmitInstruction

 1: void SampleAsmPrinter::
 2: EmitInstruction(const MachineInstr *MI) {
 3:   SampleMCInstLower MCInstLowering(OutContext, *Mang, *this);
 4:   MCInst TmpInst;
 5:   MCInstLowering.Lower(MI, TmpInst);
 6:   OutStreamer.EmitInstruction(TmpInst);
 7: }

リスト7.44: SampleMCInstLowerのクラス定義

 1: class SampleMCInstLower {
 2:   typedef MachineOperand::MachineOperandType MachineOperandType;
 3:   MCContext &Ctx;
 4:   Mangler &Mang;
 5:   AsmPrinter &Printer;
 6: 
 7:  public:
 8:   SampleMCInstLower(MCContext &ctx, Mangler &mang, AsmPrinter &printer)
 9:     : Ctx(ctx), Mang(mang), Printer(printer) {}
10:   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
11: 
12:  private:
13:   MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
14:   MCOperand LowerSymbolOperand(const MachineOperand &MO,
15:                                MachineOperandType MOTy, unsigned Offset) const;
16: };

リスト7.45: SampleMCInstLower::Lower

 1: void SampleMCInstLower::
 2: Lower(const MachineInstr *MI, MCInst &OutMI) const {
 3:   OutMI.setOpcode(MI->getOpcode());
 4: 
 5:   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 6:     const MachineOperand &MO = MI->getOperand(i);
 7:     MCOperand MCOp = LowerOperand(MO);
 8: 
 9:     if (MCOp.isValid())
10:       OutMI.addOperand(MCOp);
11:   }
12: }

リスト7.46: SampleMCInstLower::LowerOperand

 1: MCOperand SampleMCInstLower::
 2: LowerOperand(const MachineOperand& MO) const {
 3:   MachineOperandType MOTy = MO.getType();
 4:   switch (MOTy) {
 5:   case MachineOperand::MO_Register:
 6:     if (MO.isImplicit()) break;
 7:     return MCOperand::CreateReg(MO.getReg());
 8:   case MachineOperand::MO_Immediate:
 9:     return MCOperand::CreateImm(MO.getImm());
10:   case MachineOperand::MO_MachineBasicBlock:
11:   case MachineOperand::MO_GlobalAddress:
12:   case MachineOperand::MO_ExternalSymbol:
13:   case MachineOperand::MO_JumpTableIndex:
14:   case MachineOperand::MO_ConstantPoolIndex:
15:   case MachineOperand::MO_BlockAddress:
16:     return LowerSymbolOperand(MO, MOTy);
17:   case MachineOperand::MO_RegisterMask:
18:     break;
19:   default:
20:     llvm_unreachable("unknown operand type");
21:  }
22: 
23:   return MCOperand();
24: }

リスト7.47: SampleMCInstLower::LowerSymbolOperand

 1: MCOperand SampleMCInstLower::
 2: LowerSymbolOperand(const MachineOperand &MO,
 3:                    MachineOperandType MOTy) const {
 4:   switch(MO.getTargetFlags()) {
 5:     default: llvm_unreachable("Invalid target flag!");
 6:     case 0: break;
 7:   }
 8: 
 9:   const MCSymbol *Symbol;
10:   unsigned Offset = 0;
11:   switch (MOTy) {
12:   case MachineOperand::MO_MachineBasicBlock:
13:     Symbol = MO.getMBB()->getSymbol();
14:     break;
15:   case MachineOperand::MO_GlobalAddress:
16:     Symbol = Mang.getSymbol(MO.getGlobal());
17:     Offset = MO.getOffset();
18:     break;
19:   case MachineOperand::MO_BlockAddress:
20:     Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress());
21:     break;
22:   case MachineOperand::MO_ExternalSymbol:
23:     Symbol = Printer.GetExternalSymbolSymbol(MO.getSymbolName());
24:     break;
25:   case MachineOperand::MO_JumpTableIndex:
26:     Symbol = Printer.GetJTISymbol(MO.getIndex());
27:     break;
28:   case MachineOperand::MO_ConstantPoolIndex:
29:     Symbol = Printer.GetCPISymbol(MO.getIndex());
30:     Offset = MO.getOffset();
31:     break;
32:   default:
33:     llvm_unreachable("<unknown operand type>");
34:   }
35: 
36:   const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, Ctx);
37: 
38:   if (Offset) {
39:     const MCConstantExpr *OffsetExpr =  MCConstantExpr::Create(Offset, Ctx);
40:     Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
41:   }
42: 
43:   return MCOperand::CreateExpr(Expr);
44: }

リスト7.48: SampleInstPrinterのクラス定義

 1: class SampleInstPrinter : public MCInstPrinter {
 2:  public:
 3:   SampleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
 4:                   const MCRegisterInfo &MRI)
 5:     : MCInstPrinter(MAI, MII, MRI) {}
 6: 
 7:   // MCStreamerから呼び出される
 8:   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
 9:   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
10: 
11: private:
12:   // TableGenにより自動生成
13:   void printInstruction(const MCInst *MI, raw_ostream &O);
14:   static const char *getRegisterName(unsigned RegNo);
15: 
16:   // printInstructionからコールバックされる
17:   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
18:   void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
19: };

リスト7.49: SampleInstPrinter::printInst

 1: void SampleInstPrinter::
 2: printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) {
 3:   printInstruction(MI, O);
 4:   printAnnotation(O, Annot);
 5: }

リスト7.50: SampleInstPrinter::printOperand

 1: void SampleInstPrinter::
 2: printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
 3:   const MCOperand &Op = MI->getOperand(OpNo);
 4:   if (Op.isReg()) {
 5:     printRegName(O, Op.getReg());
 6:   } else if (Op.isImm()) {
 7:     O << Op.getImm();
 8:   } else {
 9:     assert(Op.isExpr() && "unknown operand kind in printOperand");
10:     O << *Op.getExpr();
11:   }
12: }

リスト7.51: SampleInstPrinter::printMemOperand

 1: void SampleInstPrinter::
 2: printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
 3:   printOperand(MI, opNum+1, O);
 4:   O << "(";
 5:   printOperand(MI, opNum, O);
 6:   O << ")";
 7: }

リスト7.52: SampleAsmBackendのクラス定義

 1: class SampleAsmBackend : public MCAsmBackend {
 2:   Triple::OSType OSType;
 3: 
 4:  public:
 5:   SampleAsmBackend(const Target &T,  Triple::OSType _OSType)
 6:     :MCAsmBackend(), OSType(_OSType) {}
 7: 
 8:   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
 9:     return createSampleELFObjectWriter(OS, OSType);
10:   }
11: 
12:   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
13:                   uint64_t Value) const;
14: 
15:   unsigned getNumFixupKinds() const { return Sample::NumTargetFixupKinds; }
16: 
17:   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
18: 
19:   bool mayNeedRelaxation(const MCInst &Inst) const {
20:     return false;
21:   }
22: 
23:   bool fixupNeedsRelaxation(const MCFixup &Fixup,
24:                             uint64_t Value,
25:                             const MCInstFragment *DF,
26:                             const MCAsmLayout &Layout) const {
27:     return false;
28:   }
29: 
30:   void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
31:   }
32: 
33:   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
34:     return true;
35:   }
36: };

リスト7.53: SampleAsmBackend::applyFixup

 1: void SampleAsmBackend::
 2: applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
 3:            uint64_t Value) const {
 4:   // 修正後の値を求める
 5:   MCFixupKind Kind = Fixup.getKind();
 6:   Value = adjustFixupValue((unsigned)Kind, Value);
 7: 
 8:   if (!Value)
 9:     return; // Doesn't change encoding.
10: 
11:   // オブジェクトのどこから修正するか
12:   unsigned Offset = Fixup.getOffset();
13:   // 何バイト修正するか
14:   unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
15: 
16:   // 現在の値を取得
17:   uint64_t CurVal = 0;
18: 
19:   for (unsigned i = 0; i != NumBytes; ++i) {
20:     unsigned Idx = i;
21:     CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
22:   }
23: 
24:   uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
25:   CurVal |= Value & Mask;
26: 
27:   // 修正後の値を書きだす
28:   for (unsigned i = 0; i != NumBytes; ++i) {
29:     unsigned Idx = i;
30:     Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
31:   }
32: }

リスト7.54: SampleAsmBackend::getFixupKindInfo

 1: const MCFixupKindInfo &SampleAsmBackend::
 2: getFixupKindInfo(MCFixupKind Kind) const {
 3:   const static MCFixupKindInfo Infos[Sample::NumTargetFixupKinds] = {
 4:     // name                  offset    bits flags
 5:     {"fixup_Sample_24",           0,     24,    0}
 6:   };
 7: 
 8:   if (Kind < FirstTargetFixupKind)
 9:     return MCAsmBackend::getFixupKindInfo(Kind);
10: 
11:   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
12:          "Invalid kind!");
13:   return Infos[Kind - FirstTargetFixupKind];
14: }

リスト7.55: SampleMCCodeEmitterのクラス定義

 1: class SampleMCCodeEmitter : public MCCodeEmitter {
 2:   SampleMCCodeEmitter(const SampleMCCodeEmitter &); // DO NOT IMPLEMENT
 3:   void operator=(const SampleMCCodeEmitter &); // DO NOT IMPLEMENT
 4:   const MCInstrInfo &MCII;
 5:   const MCSubtargetInfo &STI;
 6:   MCContext &Ctx;
 7: 
 8:  public:
 9:   SampleMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
10:                       MCContext &ctx)
11:             : MCII(mcii), STI(sti) , Ctx(ctx) {}
12:   ~SampleMCCodeEmitter() {}
13: 
14:   // 命令をバイナリにして出力する
15:   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
16:                          SmallVectorImpl<MCFixup> &Fixups) const;
17: 
18:  private:
19:   // 命令のバイナリエンコーディングを取得
20:   uint64_t getBinaryCodeForInstr(const MCInst &MI,
21:                                  SmallVectorImpl<MCFixup> &Fixups) const;
22: 
23:   // オペランドのバイナリエンコーディングを取得
24:   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
25:                              SmallVectorImpl<MCFixup> &Fixups) const;
26: 
27:   // load/storeのオペランドのバイナリエンコーディングを取得
28:   unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
29:                           SmallVectorImpl<MCFixup> &Fixups) const;
30: 
31:   // move命令のオペランドのバイナリエンコーディングを取得
32:   unsigned getMoveTargetOpValue(const MCInst &MI, unsigned OpNo,
33:                                 SmallVectorImpl<MCFixup> &Fixups) const;
34: 
35:   // call命令のオペランドのバイナリエンコーディングを取得
36:   unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
37:                                 SmallVectorImpl<MCFixup> &Fixups) const;
38: };

リスト7.56: SampleMCCodeEmitter::EncodeInstruction

 1: void SampleMCCodeEmitter::
 2: EncodeInstruction(const MCInst &MI, raw_ostream &OS,
 3:                   SmallVectorImpl<MCFixup> &Fixups) const {
 4:   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
 5: 
 6:   // 全ての命令は4バイト
 7:   int Size = 4;
 8: 
 9:   for (int i = Size - 1; i >= 0; --i) {
10:     unsigned Shift = i * 8;
11:     OS << char((Binary >> Shift) & 0xff);
12:   }
13: }

リスト7.57: SampleMCCodeEmitterのエンコード関数

 1: unsigned SampleMCCodeEmitter::
 2: getMachineOpValue(const MCInst &MI, const MCOperand &MO,
 3:                   SmallVectorImpl<MCFixup> &Fixups) const {
 4:   if (MO.isReg()) {
 5:     unsigned Reg = MO.getReg();
 6:     unsigned RegNo = getSampleRegisterNumbering(Reg);
 7:     return RegNo;
 8:   } else if (MO.isImm()) {
 9:     return static_cast<unsigned>(MO.getImm());
10:   } else if (MO.isFPImm()) {
11:     return static_cast<unsigned>(APFloat(MO.getFPImm())
12:         .bitcastToAPInt().getHiBits(32).getLimitedValue());
13:   }
14: 
15:   // Expr以外はエラー.
16:   assert(MO.isExpr());
17:   llvm_unreachable("not implemented");
18:   return 0;
19: }
20: 
21: unsigned SampleMCCodeEmitter::
22: getMemEncoding(const MCInst &MI, unsigned OpNo,
23:                SmallVectorImpl<MCFixup> &Fixups) const {
24:   // レジスタが19-16bit目，即値が15-0bit目
25:   assert(MI.getOperand(OpNo).isReg());
26:   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
27:   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
28: 
29:   return (OffBits & 0xFFFF) | RegBits;
30: }
31: 
32: unsigned SampleMCCodeEmitter::
33: getMoveTargetOpValue(const MCInst &MI, unsigned OpNo,
34:                      SmallVectorImpl<MCFixup> &Fixups) const {
35:   // 即値が19-0bit目
36:   assert(MI.getOperand(OpNo).isImm());
37:   unsigned value = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups);
38:   return value & 0xFFFFF;
39: }
40: 
41: unsigned SampleMCCodeEmitter::
42: getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
43:                      SmallVectorImpl<MCFixup> &Fixups) const {
44: 
45:   const MCOperand &MO = MI.getOperand(OpNo);
46:   assert(MO.isExpr() && "getCallTargetOpValue expects only expressions");
47: 
48:   const MCExpr *Expr = MO.getExpr();
49:   Fixups.push_back(MCFixup::Create(0, Expr,
50:                                    MCFixupKind(Sample::fixup_Sample_24)));
51:   return 0;
52: }

リスト7.58: SampleMCAsmInfoのクラス定義

 1: class SampleMCAsmInfo : public MCAsmInfo {
 2:   virtual void anchor() {};
 3:  public:
 4:   explicit SampleMCAsmInfo(const Target &T, StringRef TT);
 5: };
 6: 
 7: SampleMCAsmInfo::SampleMCAsmInfo(const Target &T, StringRef TT) {
 8:   PointerSize = 4;
 9: 
10:   PrivateGlobalPrefix = ".L";
11:   PCSymbol=".";
12:   CommentString = ";";
13: 
14:   AlignmentIsInBytes = false;
15:   AllowNameToStartWithDigit = true;
16:   UsesELFSectionDirectiveForBSS = true;
17: }

リスト7.59: SampleDisassemblerのクラス定義

 1: class SampleDisassembler : public MCDisassembler {
 2:  public:
 3:   SampleDisassembler(const MCSubtargetInfo &STI)
 4:       : MCDisassembler(STI) {}
 5: 
 6:   ~SampleDisassembler() {}
 7: 
 8:   // 命令のディスアセンブルの結果を返す
 9:   DecodeStatus getInstruction(MCInst &instr,
10:                               uint64_t &size,
11:                               const MemoryObject &region,
12:                               uint64_t address,
13:                               raw_ostream &vStream,
14:                               raw_ostream &cStream) const;
15: 
16:   const EDInstInfo *getEDInfo() const;
17: 
18: private:
19:   DecodeStatus readInstruction32(const MemoryObject &region,
20:                                  uint64_t address,
21:                                  uint64_t &size,
22:                                  uint32_t &insn) const;
23: };

リスト7.60: SampleDisassembler::getInstruction

 1: DecodeStatus SampleDisassembler::
 2: getInstruction(MCInst &instr,
 3:                uint64_t &Size,
 4:                const MemoryObject &Region,
 5:                uint64_t Address,
 6:                raw_ostream &vStream,
 7:                raw_ostream &cStream) const {
 8:   uint32_t Insn;
 9: 
10:   DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
11:   if (Result == MCDisassembler::Fail)
12:     return MCDisassembler::Fail;
13: 
14:   // TableGenによって生成された関数を呼び出す
15:   Result = decodeInstruction(DecoderTableSample32,
16:                              instr, Insn, Address, this, STI);
17:   if (Result != MCDisassembler::Fail) {
18:     Size = 4;
19:     return Result;
20:   }
21: 
22:   return MCDisassembler::Fail;
23: }

リスト7.61: SampleDisassembler::readInstruction

 1: DecodeStatus SampleDisassembler::
 2: readInstruction32(const MemoryObject &region,
 3:                   uint64_t address,
 4:                   uint64_t &size,
 5:                   uint32_t &insn) const {
 6:   uint8_t Bytes[4];
 7: 
 8:   // バイト列から4バイト読み込む
 9:   if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) {
10:     size = 0;
11:     return MCDisassembler::Fail;
12:   }
13: 
14:   // リトルエンディアンで命令をエンコーディング
15:   insn = (Bytes[3] <<  0) |
16:          (Bytes[2] <<  8) |
17:          (Bytes[1] << 16) |
18:          (Bytes[0] << 24);
19: 
20:   return MCDisassembler::Success;
21: }

リスト7.62: Operandのデコーダー

 1: // tablegenで作成したCPURegs(RegisterClass)を表示する
 2: static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
 3:                                                unsigned RegNo,
 4:                                                uint64_t Address,
 5:                                                const void *Decoder) {
 6:   if (RegNo > 31)
 7:     return MCDisassembler::Fail;
 8: 
 9:   Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
10:   return MCDisassembler::Success;
11: }
12: 
13: // load/store命令のoperandをデコード
14: static DecodeStatus DecodeMem(MCInst &Inst,
15:                               unsigned Insn,
16:                               uint64_t Address,
17:                               const void *Decoder) {
18:   int Offset = SignExtend32<16>(Insn & 0xffff);
19:   int Reg = (int)fieldFromInstruction(Insn, 16, 4);
20:   int Base = (int)fieldFromInstruction(Insn, 20, 4);
21: 
22:   Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
23:   Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
24:   Inst.addOperand(MCOperand::CreateImm(Offset));
25: 
26:   return MCDisassembler::Success;
27: }
28: 
29: // move命令のoperandをデコード
30: static DecodeStatus DecodeMoveTarget(MCInst &Inst,
31:                                      unsigned Insn,
32:                                      uint64_t Address,
33:                                      const void *Decoder) {
34:   int Offset = SignExtend32<20>(Insn & 0xfffff);
35:   int Reg = (int)fieldFromInstruction(Insn, 20, 4);
36: 
37:   Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
38:   Inst.addOperand(MCOperand::CreateImm(Offset));
39: 
40:   return MCDisassembler::Success;
41: }
42: 
43: // call命令のoperandをデコード
44: static DecodeStatus DecodeCallTarget(MCInst &Inst,
45:                                      unsigned Insn,
46:                                      uint64_t Address,
47:                                      const void *Decoder) {
48:   unsigned CallOffset = fieldFromInstruction(Insn, 0, 24) << 2;
49:   Inst.addOperand(MCOperand::CreateImm(CallOffset));
50:   return MCDisassembler::Success;
51: }

リスト7.63: LLVMInitializeSampleTargetInfo

 1: extern "C" void LLVMInitializeSampleTargetInfo() {
 2:   RegisterTarget<Triple::sample, /*HasJIT=*/false>
 3:     X(TheSampleTarget, "sample", "Sample");
 4: }

リスト7.64: LLVMInitializeSampleTarget

 1: extern "C" void LLVMInitializeSampleTarget() {
 2:   RegisterTargetMachine<SampleTargetMachine> X(TheSampleTarget);
 3: }

リスト7.65: LLVMInitializeSampleTargetMC

 1: extern "C" void LLVMInitializeSampleTargetMC() {
 2:   // MC asm infoの登録
 3:   RegisterMCAsmInfoFn X(TheSampleTarget, createSampleMCAsmInfo);
 4:   // MC codegen infoの登録
 5:   TargetRegistry::RegisterMCCodeGenInfo(TheSampleTarget,
 6:                                         createSampleMCCodeGenInfo);
 7:   // MC instruction infoの登録
 8:   TargetRegistry::RegisterMCInstrInfo(TheSampleTarget, createSampleMCInstrInfo);
 9:   // MC register infoの登録
10:   TargetRegistry::RegisterMCRegInfo(TheSampleTarget, createSampleMCRegisterInfo);
11:   // MC Code Emitterの登録
12:   TargetRegistry::RegisterMCCodeEmitter(TheSampleTarget,
13:                                         createSampleMCCodeEmitter);
14:   // object streamerの登録
15:   TargetRegistry::RegisterMCObjectStreamer(TheSampleTarget, createMCStreamer);
16:   // asm backendの登録
17:   TargetRegistry::RegisterMCAsmBackend(TheSampleTarget,
18:                                        createSampleAsmBackend);
19:   // MC subtarget infoの登録
20:   TargetRegistry::RegisterMCSubtargetInfo(TheSampleTarget,
21:                                           createSampleMCSubtargetInfo);
22:   // MCInstPrinterの登録
23:   TargetRegistry::RegisterMCInstPrinter(TheSampleTarget,
24:                                         createSampleMCInstPrinter);
25: }

リスト7.66: LLVMInitializeSampleAsmPrinter

 1: extern "C" void LLVMInitializeSampleAsmPrinter() {
 2:   RegisterAsmPrinter<SampleAsmPrinter> X(TheSampleTarget);
 3: }

リスト7.67: LLVMInitializeSampleDisassembler

 1: extern "C" void LLVMInitializeSampleDisassembler() {
 2:   TargetRegistry::RegisterMCDisassembler(TheSampleTarget,
 3:                                          createSampleDisassembler);
 4: }

リスト7.68: Sample ターゲットのMakefile(lib/Target/Sample/Makefile)

 1: LEVEL = ../../..
 2: LIBRARYNAME = LLVMSampleCodeGen
 3: TARGET = Sample
 4: 
 5: # Make sure that tblgen is run, first thing.
 6: BUILT_SOURCES = SampleGenRegisterInfo.inc SampleGenInstrInfo.inc \
 7:                 SampleGenAsmWriter.inc SampleGenCodeEmitter.inc \
 8:                 SampleGenDAGISel.inc SampleGenCallingConv.inc \
 9:                 SampleGenSubtargetInfo.inc SampleGenMCCodeEmitter.inc \
10:                 SampleGenEDInfo.inc SampleGenDisassemblerTables.inc
11: 
12: DIRS = InstPrinter Disassembler TargetInfo MCTargetDesc
13: 
14: include $(LEVEL)/Makefile.common

リスト7.69: SampleターゲットのLLVMBuild.txt(lib/Target/Sample/LLVMBuild.txt)

 1: [ common ]
 2: subdirectories = InstPrinter Disassembler MCTargetDesc TargetInfo
 3: 
 4: [component_0]
 5: type = TargetGroup
 6: name = Sample
 7: parent = Target
 8: ;has_asmparser = 1
 9: has_asmprinter = 1
10: has_disassembler = 1
11: ;has_jit = 1
12: 
13: [component_1]
14: type = Library
15: name = SampleCodeGen
16: parent = Sample
17: required_libraries = AsmPrinter CodeGen Core MC SampleAsmPrinter SampleDesc SampleInfo SelectionDAG Support Target
18: add_to_library_groups = Sample

リスト7.70: 目標のソースコード(sample_add.ll)

 1: define i32 @sample_add(i32 %a, i32 %b) nounwind readnone {
 2: entry:
 3:   %add = add nsw i32 %b, %a
 4:   ret i32 %add
 5: }

リスト7.71: 目標のソースコード(sample_call.ll)

 1: define i32 @add(i32 %a, i32 %b) nounwind readnone {
 2: entry:
 3:   %add = add nsw i32 %b, %a
 4:   ret i32 %add
 5: }
 6: 
 7: define i32 @sample_call() nounwind readnone {
 8: entry:
 9:   %call = tail call i32 @add(i32 1, i32 2)
10:   ret i32 %call
11: }

リスト7.72: sample_add.s

 1:         .file   "sample_add.ll"
 2:         .text
 3:         .globl  sample_add
 4:         .align  2
 5:         .type   sample_add,@function
 6: sample_add:                             ; @sample_add
 7: ; BB#0:                                 ; %entry
 8:         move    $t0, -64
 9:         add     $sp, $sp, $t0
10:         store   $ra, 60($sp)            ; 4-byte Folded Spill
11:         add     $a0, $a1, $a0
12:         add     $v0, $zero, $a0
13:         load    $ra, 60($sp)            ; 4-byte Folded Reload
14:         move    $t0, 64
15:         add     $sp, $sp, $t0
16:         ret     $ra
17: .Ltmp0:
18:         .size   sample_add, .Ltmp0-sample_add

リスト7.73: sample_add.s(ダンプ付き)

 1:         .file   "sample_add.ll"
 2:         .text
 3:         .globl  sample_add
 4:         .align  2
 5:         .type   sample_add,@function
 6: sample_add:                             ; @sample_add
 7: ; BB#0:                                 ; %entry
 8:         move    $t0, -64                ; encoding: [0x02,0x6f,0xff,0xc0]
 9:                                         ; <MCInst #22 MOVE
10:                                         ;  <MCOperand Reg:11>
11:                                         ;  <MCOperand Imm:-64>>
12:         add     $sp, $sp, $t0           ; encoding: [0x05,0xee,0x60,0x0e]
13:                                         ; <MCInst #17 ADD
14:                                         ;  <MCOperand Reg:10>
15:                                         ;  <MCOperand Reg:10>
16:                                         ;  <MCOperand Reg:11>>
17:         store   $ra, 60($sp)            ; 4-byte Folded Spill
18:                                         ; encoding: [0x01,0xfe,0x00,0x3c]
19:                                         ; <MCInst #24 STORE
20:                                         ;  <MCOperand Reg:5>
21:                                         ;  <MCOperand Reg:10>
22:                                         ;  <MCOperand Imm:60>>
23:         add     $a0, $a1, $a0           ; encoding: [0x05,0x23,0x20,0x02]
24:                                         ; <MCInst #17 ADD
25:                                         ;  <MCOperand Reg:1>
26:                                         ;  <MCOperand Reg:2>
27:                                         ;  <MCOperand Reg:1>>
28:         add     $v0, $zero, $a0         ; encoding: [0x05,0x10,0x20,0x01]
29:                                         ; <MCInst #17 ADD
30:                                         ;  <MCOperand Reg:15>
31:                                         ;  <MCOperand Reg:16>
32:                                         ;  <MCOperand Reg:1>>
33:         load    $ra, 60($sp)            ; 4-byte Folded Reload
34:                                         ; encoding: [0x00,0xfe,0x00,0x3c]
35:                                         ; <MCInst #21 LOAD
36:                                         ;  <MCOperand Reg:5>
37:                                         ;  <MCOperand Reg:10>
38:                                         ;  <MCOperand Imm:60>>
39:         move    $t0, 64                 ; encoding: [0x02,0x60,0x00,0x40]
40:                                         ; <MCInst #22 MOVE
41:                                         ;  <MCOperand Reg:11>
42:                                         ;  <MCOperand Imm:64>>
43:         add     $sp, $sp, $t0           ; encoding: [0x05,0xee,0x60,0x0e]
44:                                         ; <MCInst #17 ADD
45:                                         ;  <MCOperand Reg:10>
46:                                         ;  <MCOperand Reg:10>
47:                                         ;  <MCOperand Reg:11>>
48:         ret     $ra                     ; encoding: [0x04,0xf0,0x00,0x0f]
49:                                         ; <MCInst #23 RET
50:                                         ;  <MCOperand Reg:5>>
51: .Ltmp0:
52:         .size   sample_add, .Ltmp0-sample_add

リスト7.74: sample_call.s

 1:         .file   "sample_call.ll"
 2:         .text
 3:         .globl  add
 4:         .align  2
 5:         .type   add,@function
 6: add:                                    ; @add
 7: ; BB#0:                                 ; %entry
 8:         move    $t0, -64
 9:         add     $sp, $sp, $t0
10:         store   $ra, 60($sp)            ; 4-byte Folded Spill
11:         add     $a0, $a1, $a0
12:         add     $v0, $zero, $a0
13:         load    $ra, 60($sp)            ; 4-byte Folded Reload
14:         move    $t0, 64
15:         add     $sp, $sp, $t0
16:         ret     $ra
17: .Ltmp0:
18:         .size   add, .Ltmp0-add
19: 
20:         .globl  sample_call
21:         .align  2
22:         .type   sample_call,@function
23: sample_call:                            ; @sample_call
24: ; BB#0:                                 ; %entry
25:         move    $t0, -64
26:         add     $sp, $sp, $t0
27:         store   $ra, 60($sp)            ; 4-byte Folded Spill
28:         move    $a0, 1
29:         move    $a1, 2
30:         call    add
31:         load    $ra, 60($sp)            ; 4-byte Folded Reload
32:         move    $t0, 64
33:         add     $sp, $sp, $t0
34:         ret     $ra
35: .Ltmp1:
36:         .size   sample_call, .Ltmp1-sample_call

リスト7.75: sample_add.oのディスアセンブル

 1: sample_add.o:   file format ELF32-unknown
 2: 
 3: Disassembly of section .text:
 4: .text:
 5:        0:       02 6f ff c0               move    $t0, -64
 6:        4:       05 ee 60 0e               add     $sp, $sp, $t0
 7:        8:       01 fe 00 3c               store   $sp, 60($ra)
 8:        c:       05 23 20 02               add     $a0, $a1, $a0
 9:       10:       05 10 20 01               add     $v0, $zero, $a0
10:       14:       00 fe 00 3c               load    $sp, 60($ra)
11:       18:       02 60 00 40               move    $t0, 64
12:       1c:       05 ee 60 0e               add     $sp, $sp, $t0
13:       20:       04 f0 00 0f               ret     $ra

リスト7.76: sample_call.oのディスアセンブル

 1: sample_call.o:  file format ELF32-unknown
 2: 
 3: Disassembly of section .text:
 4: .text:
 5:        0:       02 6f ff c0               move    $t0, -64
 6:        4:       05 ee 60 0e               add     $sp, $sp, $t0
 7:        8:       01 fe 00 3c               store   $sp, 60($ra)
 8:        c:       05 23 20 02               add     $a0, $a1, $a0
 9:       10:       05 10 20 01               add     $v0, $zero, $a0
10:       14:       00 fe 00 3c               load    $sp, 60($ra)
11:       18:       02 60 00 40               move    $t0, 64
12:       1c:       05 ee 60 0e               add     $sp, $sp, $t0
13:       20:       04 f0 00 0f               ret     $ra
14:       24:       02 6f ff c0               move    $t0, -64
15:       28:       05 ee 60 0e               add     $sp, $sp, $t0
16:       2c:       01 fe 00 3c               store   $sp, 60($ra)
17:       30:       02 20 00 01               move    $a0, 1
18:       34:       02 30 00 02               move    $a1, 2
19:       38:       03 00 00 00               call    0
20:       3c:       00 fe 00 3c               load    $sp, 60($ra)
21:       40:       02 60 00 40               move    $t0, 64
22:       44:       05 ee 60 0e               add     $sp, $sp, $t0
23:       48:       04 f0 00 0f               ret     $ra